Main memories of computer systems are generally formed using dynamic semiconductor memory chips (DRAM). For this purpose, a number of memory chips are combined on a small circuit board as a memory module. At least a portion of such memory modules then forms the main memory.
In the case of high-quality computer systems, such as network servers or workstations, the memory must be comparatively free of errors compared to a relatively simple computer system such as a desktop computer. All RAM memories experience occasional errors due to factors such as power fluctuations, static electricity discharges, faulty components or improper system timing. However, in some computer systems the stored data should be relatively free from errors. For this reason, these computer systems have so-called error correction devices which, upon storage of data in the main memory, generate one or more error correction bits (ECC bits or ECC information) per data record and transfer this information so that it is stored together with the data to be stored in the main memory. Correspondingly, when data stored in the main memory are read out, the associated ECC information is also read out and transferred to an error correction device for corresponding evaluation and, if necessary, error recovery.
So far, the focus of memory manufacturers has only been on non-ECC future DRAMs. In these DRAMs, an error correction code information is not stored together with the data. Additionally, a protocol has been defined for this non-ECC DRAM type. The protocol determines the structure of the data to be stored in the DRAM.
However, the current protocol definition does not allow inclusion of ECC information. Instead, to include this information the protocol, general frame structure, or pin count must be completely changed. Such changes lead to major architectural changes and to different architectures for non-ECC and ECC DRAMs. This is a serious cost factor, as different protocols would then be implemented for the different types of DRAMs.
It is thus apparent that a need exists to provide addressing of a data memory with a single type of protocol.